Central Processing Unit (CPU)

— Computer Science · AS Level (9618) · Processor Fundamentals —

★ Exam Tip: This is a memory-based chapter — understand each point, relate it to something real, then write it in your own words. Questions are usually 2–4 marks ("Explain the control unit", "Explain the status register and CIR"). No negative marking — always write all the points you know. For topics new to the 9618 syllabus (cache, cores, HDMI, VGA) the mark scheme is unknown, so write as much correct content as you can.

1. Von Neumann Architecture

one shared memory holds BOTH data and program

Definition: The Von Neumann architecture consists of a single, shared memory for program and data.

Main parts: ① CPU (control unit + ALU + registers) · ② Memory · ③ Input / Output devices. Think of it like the human body — the CU is the brain, directing everything.

Data = values (e.g. A = 10) | Program = instructions (e.g. ADD) that work on that data. Von Neumann keeps both in the same memory.

Note (not in syllabus): Harvard architecture does the opposite — separate memories for data and program. Von Neumann is what you need. Don't draw this diagram in the exam unless asked; you may be asked to label a similar one.

2. Control Unit (CU)

Directs and co-ordinates other parts of the computer system (sends signals to hardware, buses, I/O)
Controls operations of the computer system
Fetches computer instructions
Decodes each instruction (so the computer can understand it)
Executes these instructions

Remember: CU = brain.
Fetch → Decode → Execute are the 3 steps (more detail in the fetch-execute cycle).

★ Exam Tip: "Explain the control unit" is usually a 3–4 mark question. Write all 5 points — extra correct points are your safety net.

3. Arithmetic Logic Unit (ALU)

The name gives you both jobs — Arithmetic + Logic. Always write every point.

A unit which performs arithmetic operations ( + − × ÷ )
and bit-shifting operations (left shift, right shift)
Logic operations (AND, OR, XOR)
Designed to perform integer calculations

Link it: Inside the ALU are logic circuits — adders (add bits/numbers) and subtractors (A2 "Logic gates"). Multiplication = repeated addition (2 × 3 → 2 + 2 + 2), so adders do that too.

4. Operand & Opcode

Operand: part of the computer instruction which specifies what data is to be processed (either the data itself or the address of the data).

Opcode: is the instruction that is executed by the CPU (what to do to the data).

Example:

ADD 40 → opcode = ADD (the operation), operand = 40 (the data it works on).

5. Registers

Small piece of memory
Part of the processor
Temporary storage of data which is about to be / has been processed

Why registers? The CPU is much faster than main memory, so they can't keep the same pace. Registers are tiny but very fast memory (a few bits — built from flip-flops, A2). Data is moved into registers and the CPU takes it from there.

data travels HDD → RAM → registers → CPU

General purpose vs special purpose registers

General purpose registers	Special purpose registers
Hold the temporary data while performing different operations	Hold the status of a program (not data being processed)
e.g. ACC (accumulator)	e.g. PC, MAR, MDR, CIR, status register

★ Exam Tip: If this is a 3–4 mark question, always give examples — examples earn marks! GPR → ACC (used in assembly language). SPR → PC, MAR, MDR, CIR, status register. Two bare definitions alone get only ~2 marks.

6. Special Purpose Registers

You must be able to explain the purpose of each. Relate them to this example — memory contents and the registers during a fetch:

MAR holds an address (401) → MDR gets what is at that address (40) → CIR holds the instruction being run (ADD) → PC points at the next one (403)

Register	Stores…
PC — Program Counter	the address of the next instruction to be fetched
MAR — Memory Address Register	the memory address where data is to be read from
MDR — Memory Data Register	the data that has just been read from memory
CIR — Current Instruction Register	the instruction that is currently being executed
IX — Index Register	used for indirect addressing (see assembly language)
ACC — Accumulator	the register where the data is worked on (a general purpose register)
Status register	is interpreted as independent flags; each flag is set depending on an event

Remember: the names themselves give the answer — Memory Address Register → stores a memory address. Forgot a definition? Rebuild it from the name!

Trick (walk through the example): "Add 40 to the accumulator." Data lives at 401 → MAR = 401 (where to read from). CPU fetches it → MDR = 40. Instruction to run is ADD → CIR = ADD. Next instruction's address → PC.
Order of running follows the assembly program's sequence, not memory-address order (jumps/branches can go anywhere).

Accumulator (ACC): every add, subtract, increment, decrement result sits temporarily in ACC while being processed; to keep it permanently you STOre it to an address (assembly instruction).

Status register: works like a set of flags (each 0 or 1) that record the state of the CPU / a program, e.g. the interrupt flag. It stores status, not data.

★ Exam Tip: Examiners may say "Explain the status register and the CIR" or "the control unit and the ALU" — explain each separately using the points above.

7. System Clock

Every computer contains an internal clock that regulates the rate at which the instructions are executed
The CPU requires a fixed number of clock cycles to execute each instruction
Used to synchronise all the operations

Some instructions take 1 cycle, others 5, 6, 7 … — the clock keeps everything in step. Clock speed = how many cycles/pulses per second, measured in hertz (Hz) — e.g. 2.2 GHz = about 2.2 billion cycles every second. It differs from CPU to CPU.

Common mistake: Don't just say "it measures speed". Write all three points: regulates the rate of execution, a fixed number of cycles per instruction, and synchronises operations.

8. Buses — How data moves between components

Question: How is data transferred between the various components of the computer system? → using three buses (sets of wires): data, address, control.

Bus	Direction	What it carries
Data bus	Bi-directional (two-way)	Carries data between processor and memory; used to exchange data (give + take)
Address bus	Uni-directional (one-way)	Carries signals related to memory addresses between processor and memory
Control bus	Bi-directional	Transmits signals between the control unit and other components

Trick: Bi = two (→ ←), Uni = one. Say "bi-directional" for the data bus because data is both sent and received (exchange). Bi-directional is drawn with two arrows (up and down) or one arrow with heads at both ends.

Note (board discrepancy): The theory box on the board says the control bus is bi-directional, but the picture-question key points (below) draw it as a one-way arrow. For a theory answer write "bi-directional" (as in the theory notes); for the picture question use the identification clues below. The teacher also said address bus is unidirectional in theory — stick with that.

9. Components & Buses inside a Typical Computer

redrawn from the board — address bus (red) touches CU + memory + GPR · data bus (green) ONLY memory ↔ GPR · control bus (purple) joins the CU

Key points to consider while solving a picture question

ALU & CU will have a direct bi-directional connection ⟷
Main memory will have a direct connection with the general purpose registers ⟷ (two-headed arrow)
System clock will have a uni-directional connection → CU (arrowhead points at the control unit)
Data bus (bi-directional): it will only have a connection with memory and general purpose registers
Control bus: drawn as a uni-directional arrow ⟶ on the board; it is the one linked with the control unit (signals between CU and other components)
Address bus will be connected from main memory till the GPR and it will also have a connection with the control unit

★ Exam Tip: Don't redraw this diagram — study it from your notes. The examiner may blank a box (a letter instead of "Control Unit") or a bus and ask what goes there. Make your own key points: e.g. the box that the clock's arrow points to = CU; a double-headed arrow touching only memory and GPR = data bus; a bus that also touches the CU = address bus (or control bus). The more of these you practise, the faster you identify.

10. Factors Affecting Computer Performance

9608 had only bus width and clock speed. 9618 added cache memory and number of cores (cores has already been asked; cache not yet). Learn all 4, three points each.

① Data bus width

The width of a bus determines the number of bits that can be simultaneously transferred
Increasing the width of a data bus increases the number of bits that can be transferred
Hence improves processing speed as fewer transfers are needed

narrow bus ✗ slower

wide bus ✓ faster

"Fewer transfers": if 5 bits move per transfer, 15 bits need 3 transfers; a wider bus moves more per transfer → fewer transfers needed → processing speed increases.

② Clock speed

One F-E cycle is run on each clock pulse
So the clock speed dictates the number of instructions that can be run per second
The faster the clock speed, the more instructions can be run per second
So the processing speed would increase

Real-life limit: Raising (over-clocking) the clock speed makes the CPU hot — you need strong fans/air-flow. Reducing (under-clocking) lowers heat but slightly lowers speed. That is why speed can't just be pushed to the maximum.

Clock speed measured in Hz (GHz = billions of pulses/second). Don't try software over-clocking tools without knowledge — you can burn the CPU.

③ Cache memory

Can also improve processor performance; it is similar to RAM — cache uses SRAM
So it has a faster access time as there is no need to keep refreshing
Cache memory stores frequently used instructions and data that need to be accessed faster
This improves processor performance

Repeated instructions are kept in this small, fast temporary memory so the CPU doesn't wait for slower main memory each time.

④ Number of cores

Each core processes one instruction per clock pulse
More cores mean the sequence of instructions can be split between them, so more than one instruction is executed per clock pulse
More cores decreases the time taken to complete a task

1 core ✗ slow

2 cores ✓ time halved

Link it (A2): Each core has its own ALU, registers and control unit. Splitting instructions across cores links to pipelining — several instructions in different stages at once (you'll study it in A2).

11. Ports

Acts as an interface between computers and other peripheral devices (input/output devices)
The female part of the connection — the cable end plugs into it

USB — benefits of connecting peripheral devices using a USB port

How marks work: Points in red = the state mark, blue = the explain mark. For "describe/explain" write both; treat each pair as a single point to stay safe. USB questions have appeared often in past papers.

Benefit (state)	Explain
Fast data transfer	useful when transferring large files such as video files (very high speed)
Automatic connection / Plug and Play	so usually there is no need to install separate drivers (drivers tell the PC what the device's buttons/functions do; USB drivers are already built in)
USB is now an industrial standard	All new computers will be equipped with a USB port (every manufacturer includes one)
Device may be powered or charged through USB	External devices could be charged while working at the computer — USB carries data and power (fibre optic carries only data)

High Definition Multimedia Interface (HDMI)

Helps to connect more monitors
HDMI ports allow to output both audio and visual
They support high definition signals
Faster data transfer
HDMI increases the bandwidth, making it possible to supply the necessary data for high quality sound and visual effects

old PS2-style AV: separate yellow (video) + white/red (sound) leads · HDMI: one cable does both

Advantages of HDMI

Current standard for modern televisions and monitors
Allows for a very fast data transfer rate
Improved security, helps prevent piracy by the help of HDCP
Supports modern digital systems

Disadvantages of HDMI

Not a very robust connection (easy to break the connection when simply moving devices — the head bends/breaks)
Limited cable length

HDCP: an extension of HDMI that protects content — only authorised devices can display it. Piracy = using someone's content without ownership / credit. Newer curved monitors, high refresh rates, and "99% of new laptops" use HDMI.

Video Graphics Array (VGA)

Blue 15-pin connector with two screws to fix it in place. Learn both lists — write as much as you can (mark scheme unknown).

Advantages of VGA

Simpler technology (old, so lots of information/resources)
Only one standard available (unlike USB 2.0 / 3.0)
Easy to split the signals (splitter) and connect a number of devices from one source — e.g. 3–4 monitors
The connection is very secure (screws hold it in)
VGA supports a higher refresh rate (about 60 Hz, though lower than HDMI)

Disadvantages of VGA

It does not support audio (video only)
Outdated — modern laptops and computers rarely have a VGA port
Easy to bend the pins when making connections

Note: VGA is still found where only video is needed (e.g. office projectors). A VGA ⟷ HDMI converter can join old and new equipment.

12. Fetch-Execute Cycle

Uses the registers — learn the order like a story, in your own words. Data starts on HDD → RAM → registers.

PC holds the address of the next instruction to be fetched
The address in the program counter is copied to the MAR
The program counter is incremented (by 1 — ready for the next instruction)
The instruction is copied from the address stored in MAR to the MDR
Then the instruction from the MDR is copied to the CIR

① PC → MAR · ② PC + 1 · ③ memory at address MAR → MDR · ④ MDR → CIR

Register-transfer notation (RTN)

MAR ← [PC]
PC ← [PC] + 1
MDR ← [[MAR]]
CIR ← [MDR]

Read it as: ← "gets / is copied from" | [X] = contents of X | [[X]] = contents of the address held in X

Walk-through with numbers: PC holds 401 → copied to MAR (MAR = 401). PC becomes 402 (next instruction). Go to address 401, take what is stored there (e.g. 40 / an instruction like INC) → MDR. If it is an instruction, it moves on to the CIR; if it is data, it stays in the MDR.

Board questionShort answer · RTN

The third instruction MDR ← [[MAR]] has double brackets. State the purpose of the double brackets.

Idea: MAR holds an address, not the data — we need what is at that address.

Answer: The content of MAR is an address; it is the contents of that address which is transferred to MDR.

★ Exam Tip — how the examiner plays with this: they may remove double brackets, change +1 to −1 (PC is only ever incremented → "+"), reverse an arrow, or blank a register ("fill in the blank: MDR") and ask "what is the error?". Don't rote-learn the notation — know the process (the 5 points) and you can fix any altered line. Also write 5 points if asked to "explain the fetch-execute cycle".

13. Concept of Interrupt

What is meant by interrupt?

A signal from a source / device
Telling the processor that its attention is needed

"Interrupt" = a break/stoppage. Something more urgent interrupts the work being done, e.g. battery about to die while a lecture is running → interrupt signal → processor attends to it first.

Hardware interrupt

Printer out of paper
No CD in drive
(also: USB not detected, mouse not connecting)

Software interrupt

Run-time error
A running program needs input
(also: logic / programming errors)

★ Exam Tip: In AS you'll be given an example and asked to identify it as hardware or software interrupt. If it mentions a physical device (mouse, printer, USB, CD drive) → hardware. If it's about an application / program / programming error → software.

Explain how the processor handles an interrupt (5–6 marks)

At the start of each fetch-execute cycle the processor checks for interrupt
Checks if an interrupt flag is set (flag 0 = no interrupt, 1 = interrupt)
Processor identifies the source of the interrupt
Processor checks the priority of the interrupt
If interrupt priority is high enough, the lower priority interrupts are disabled
Processor saves the current content of registers
Processor calls the ISR (Interrupt Service Routine)
The address of the ISR is loaded in the PC (Program Counter)
When servicing of the interrupt is complete, the processor restores the registers
Lower priority interrupts are re-enabled
Processor continues the F-E cycle

the whole interrupt "story" at a glance — the cycle repeats until all interrupts are dealt with

Trick — learn it as a story, in your own words: don't memorise word-for-word (that puts pressure on you); keep the logic and rewrite it. Before every cycle → check flag → who sent it? → how urgent? → pause lower ones → save my work → call the fixer (ISR) → give its address to PC → fix → restore my work → un-pause the others → carry on.

Why disable lower-priority ones? So the interrupt being handled isn't itself interrupted by a less important one (like a thief being interrupted by another thief mid-job!).

ISR = Interrupt Service Routine — the "solution" for that particular interrupt. Every interrupt has its own ISR (battery problem → battery ISR; paper jam → printer ISR). They are listed in an interrupt dispatch table, and each interrupt has a priority level (1, 2, 3 …) — details in A2.

Q: Why is the ISR's address loaded in the PC and not directly into MAR? Because the interrupt is handled with the same fetch-execute cycle: PC → MAR → MDR → CIR. The ISR's instructions are fetched like any other instruction, so its address goes in the PC first.

★ Exam Tip: This is a 5–6 mark question and the mark scheme can't be predicted — write as many of the 11 points as you can. Time isn't a problem in the theory papers, so always write more content.

Board questionShort answer

Give three different events that can generate an interrupt.

1 ✓ Hardware faults 2 ✓ I/O requests 3 ✓ Software errors

Just name the events. Others that fit: USB not detected / driver missing, peripheral (I/O) device request, programming or run-time errors.

Answer: hardware faults · I/O requests · software errors

Quick Recap — Full Chapter Cheat-Sheet

✓ Components & definitions

Von Neumann: single shared memory for program and data
CU: directs & co-ordinates · controls operations · fetches, decodes, executes instructions
ALU: arithmetic (+ − × ÷) · bit shifting · logic (AND, OR, XOR) · integer calculations
Operand = what data is processed · Opcode = instruction executed by CPU
Register: small piece of memory, part of processor, temporary storage. GPR = temporary data during operations (ACC) · SPR = status of a program (PC, MAR, MDR, CIR, status reg.)
PC address of next instruction · MAR address data is read from · MDR data just read · CIR instruction being executed · IX indirect addressing · ACC where data is worked on · Status reg. independent flags set by events
System clock: regulates rate of instruction execution · fixed number of cycles per instruction · synchronises all operations

✓ Buses & performance

Data bus bi-directional, processor ⟷ memory (only memory + GPR in diagrams) · Address bus uni-directional, memory addresses · Control bus signals between CU and other components
Diagram clues: ALU ⟷ CU · memory ⟷ GPR · clock → CU (one-way) · address bus also touches CU
Bus width ↑ → more bits per transfer → fewer transfers · Clock speed ↑ → more F-E cycles/sec (limit = heat) · Cache (SRAM, no refresh) holds frequently used data/instrs · More cores → more instrs per clock pulse, less time

✓ Ports

Port = interface between computer and peripherals, female connector
USB: fast transfer · plug & play (no drivers) · industrial standard · power/charge devices
HDMI + current standard · fast · HDCP security · modern digital · audio + video, HD, more monitors − not robust · limited cable length
VGA + simple · one standard · easy to split · secure (screws) · higher refresh rate − no audio · outdated · pins bend

✓ Fetch-execute & interrupts

MAR ← [PC] · PC ← [PC] + 1 · MDR ← [[MAR]] · CIR ← [MDR] (double brackets = contents of the address held in MAR)
Interrupt = signal from a source/device telling the processor its attention is needed. Hardware: printer out of paper, no CD · Software: run-time error, program needs input
Handling: check flag at start of each F-E cycle → identify source → check priority (disable lower) → save registers → call ISR → ISR address in PC → restore registers → re-enable lower → continue F-E
3 events: hardware faults · I/O requests · software errors